library verilog;
use verilog.vl_types.all;
entity Conv is
    port(
        clock_27        : in     vl_logic;
        clock_50        : in     vl_logic;
        borda           : in     vl_logic;
        binarizacao     : in     vl_logic;
        mostra_gray     : in     vl_logic;
        reset           : in     vl_logic;
        thrashhold      : in     vl_logic_vector(9 downto 0);
        pixel           : in     vl_logic_vector(9 downto 0);
        pixel_valido    : in     vl_logic;
        pixel_convoluido: out    vl_logic_vector(9 downto 0)
    );
end Conv;
